Research > Projects


FOUTICS logo(Fr – ANR)


The aim of the FOUTICS project is to propose full-stack, open-source methods and tools to train and infer ultra-lightweight AIs, by extending, implementing, and optimizing Tangled Program Graphs (TPGs).
Exploiting the TPG efficiency and integrating energy optimization at its core, FOUTICS will create methodologies to implement energy efficient AI, capable of nanoseconds reaction time on hardware platforms ranging from Ultra-Low Power embedded devices to reconfigurable devices. Extending TPGs to new learning environments, FOUTICS will enable real world Cyber-Physical System use cases and will optimize energy use from training to physical execution on the factory floor.
INSA Rennes (leader)
Dark Era logo(Fr – ANR)


The Dark Era ANR project aims at tackling some of the High-Performance Computing (HPC) challenge behind the Square Kilometer Array (SKA) exascale radio telescope. Objectives of the project are:

  1. Building SimSDP, a rapid prototyping tool providing exascale simulations from dataflow algorithm description.
  2. Exploring low power accelerators like FPGA or Kalray MPPA as alternatives to mainstream GPU architecture.
  3. Being source of proposals for SKA computing and promoting French contributions to the international SKA consortium.
L2S (leader), INSA Rennes, IRISA, Observatoire de Nancay, Lagrange, Atos


Cerbero logo(EU – H2020)


The CERBERO EU project aims at developing a design environment for Cyber-Physical Systems based on two pillars:

  1. A cross-layer model-based approach to describe, optimize, and analyze the system and all its different views concurrently, and
  2. An advanced adaptivity support based on a multi­layer autonomous engine.

The targeted three applications of CERBERO are a self­-healing system for planetary exploration, unmanned vehicles for ocean monitoring and a smart travel network for electric vehicles.

IBM (leader), UniSS, Thales Alenia Space, UniCA, INSA Rennes, UPM, Università della Svizzera Italiana, Abinsula, Ambiesense, TNO, S&T, and Centro Ricerche Fiat
Mordred logo(Fr – GdR ISIS)


The objective of the Mordred young researcher project is to create a set of methods and tools to ease the design and implementation of applications for massively parallel architecture. The project has two main research axes:

  1. The design of a reconfigurable stereo-matching algorithm. This implementation based on dataflow models of computations will be specifically design to offer high performance on massively parallel architectures, by exploiting temporal redundancy of analyzed stereo-video streams.
  2. The porting of the Spider runtime on the Kalray MPPA256 massively architecture. The Spider runtime is a dataflow aware RTOS specifically designed to manage the execution of reconfigurable PiSDF graphs onto embedded Multiprocessor Systems-on-Chips.
IETR (leader), Lab-STICC
(US – NSF)
This project will develop new techniques to help advanced computing systems for signal processing better adapt to the environments in which they operate.
UMD (leader), National Chung Tiao University, INSA, Georgia Tech.
Artefact logo(Fr/CH – ANR/FNSNF)


The ARTEFaCT project aims to ease the design of energy efficient circuits by using approximate computing techniques. The project will contribute along three main research directions:

  1. Approximate, ultra low-power circuit design,
  2. Modeling and analysis of variable levels of computation precision in applications
  3. Accuracy-energy trade-offs in software.
CEA Leti (leader), EPFL, INRIA, INSA
compa logo(FR – ANR)


The goal of the COMPA project is to propose generic models for adaptive multi-processors embedded systems. The project proposes:

  • To target independent description of the application, with a focus on dataflow Model of Computations (MoC).
  • To offer additional opportunities for optimizing the application implementation, by developing a static analysis toolbox for detecting underlying MoCs used in a given CAL description.
  • To specify and develop a “Runtime Execution Engine” which will be in charge of the execution of the dataflow network on the platform.

All these contributions have been integrated in an open source software suite and a set of “runtime manager” software components have been developed for a multi-core FPGA based hardware demonstrator.

INSA (leader), Texas Instruments France, Lab-STICC, IRISA, CAPS Entreprise, Modae